The current development trend of semiconductor packaging is to develop more and more high-frequency, multi-chip module (MCM), system integration (SiP) packaging, and stacked packaging (PiP, PoP). As a result, the traditional assembly level is becoming more and more blurred. The integration between semiconductor assembly and traditional circuit board assembly, such as flip chip (Flip Chip) is directly assembled in the end product. The characteristic functions in semiconductor assembly equipment began to appear on the multi-functional fine-pitch placement machine, with high precision and the function of flux application. It can be said that the component stacking technology is developed on the mature flip-chip assembly technology.

 

 

Since 2003, most of the component stacking technology has only been applied to flash memory and some mobile memory cards. In 2004, the stacking assembly between the logic operation unit and the storage unit of the mobile phone began to appear. In this fiscal year, the average growth rate of the entire stacking technology market reached 60%. It is estimated that the growth rate will reach 21% in 2009, and the application of stacking assembly technology for mobile phones will account for 17% of the entire technology market. 3G mobile phones and MPEG4 will use this technology in large quantities.

The key to mobile communication products is to solve the problem of "bandwidth", in layman's terms, it is the ability to process signals at a high speed. This requires a new type of digital signal processor. One of the solutions is to place a memory (usually a dynamic memory) on the logic controller to achieve miniaturization and enhanced functions. The mature flip chip technology has contributed to the possibility of a large number of applications of this technology. Basically, we can use the existing SMT existing and downstream resources and the ready-made logistics supply chain to introduce this technology for mass production.

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Most of the stacking of chips in the components adopts wire bonding (Wire Bonding), and the number of stacking layers can be from 2 to 8 layers. STMICRO claims that so far 40 micron chips can be stacked from two to eight (SRAM, flash, DRAM), 8 40 micron chips are stacked with a total thickness of 1.6mm, and two stacked with a thickness of 0.8mm.

Device built-in device (PiP, Package in Package), the chip in the package is stacked on the substrate by gold wire bonding, and the same stack is bonded by the gold wire to the substrate between the two stacks, and then the entire package is packaged into one component. PiP (device built-in device). The PiP package has a low profile height and can use standard SMT circuit board assembly processes, and the assembly cost of a single device is low. However, since a single chip cannot be tested individually before packaging, the total cost will be high (package yield problem), and the memory structure needs to be determined in advance. The device can only be determined by the design service company, and there is no freedom of choice for the end user.

Component stacking assembly (PoP, Package on Package), where components are placed on top of the bottom component. Logic + storage is usually 2 to 4 layers, and storage PoP can reach 8 layers. The profile height will be slightly higher, but each device can be tested individually before assembly, ensuring a higher yield, and the total stacking assembly cost can be minimized. The combination of devices can be freely selected by the end user. For 3G mobile phones, digital cameras, etc., this is the preferred assembly solution.

 

The focus of PoP assembly is to control the spatial relationship between components. If there is no proper gap between them, there will be stress, which has a fatal impact on reliability and assembly yield. To sum up, its spatial relationship has the following which need our attention:

Molding height of bottom device

The height and pitch of the solder balls before reflow of the top device

Before reflow, the gap between the bottom surface of the top device and the top surface of the bottom component

The height and spacing of the solder balls after the top device is reflowed

After reflow, the gap between the bottom surface of the top device and the top surface of the bottom component

 

In addition to the substrate and component design, the factors affecting the spatial relationship include substrate manufacturing process, component packaging process and SMT assembly process. The following aspects need to be paid attention to:

Pad design

Solder mask window

Solder ball size

Ball height difference

The amount of flux or solder paste dipped

Placement accuracy

Reflow environment and temperature

Warpage of components and substrates

Molding thickness of bottom device