As we all know, various USB interfaces, emulation downloader interfaces, and other plug-in devices, due to the external mechanical stress applied during plug-in and plug-in, will affect other surrounding devices and PCB boards, causing reliability problems such as potential failures, such as: The solder ball on the PCB is cracked, the circuit is damaged, the pad is lifted, the substrate is cracked; the components are broken, and the function test is poor.

 

 

Stress improvement can be started from the design side, production side, etc., in which the stress design can be effectively improved in the PCB design stage, such as:

1. Layout the plug-in devices on the central symmetry axis of the circuit board;

2. Control the distance between stress-sensitive components and plug-in devices;

3. Keep a certain distance between the pad of the stress-sensitive component and the V-CUT line, stamp hole, and even the connection point.

A good stress design can effectively improve manufacturability and reduce the risks of unqualified mass assembly, product quality degradation, and quality problems. But the problem is that it is easy to overlook this aspect in the PCB design process. How to effectively ensure that designers fully consider stress issues during the R&D phase and implement them in place is of great concern to R&D and quality departments.

Today I will introduce to you an artifact that is used by benchmark companies in various electronics industries. Maybe it is the artifact that allows companies to widen the reliability gap. It is included in the recommended list of reliability improvement technology solutions released by the Ministry of Industry and Information Technology at the end of last year.